Content-addressablememory (CAM) is a type of associative memory, which returns the address\nof a given search input in one clock cycle. Many designs are available to emulate the CAM functionality\ninside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access\nmemory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in\nsoftware defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM\nconsume much dynamic power owing to a high amount of switching activity and computation involved\nin finding the address of the search key. In this paper, we present a power and resource efficient binary\nCAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available\narchitectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is\nactivated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables\n(LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64*36\nwhich improved power consumption and hardware cost by 30 and 32%, respectively, compared to the\navailable FPGA-based CAMs.
Loading....